1. Field of the Invention
The present invention generally relates to a chip scale package (CSP), and more particularly, to a method of manufacturing chip scale package at wafer level for accurately dividing the wafer into individual chips.
2. Description of the Related Art
As electronic devices have become smaller and thinner, the velocity and the complexity of IC chip become more and more higher. Accordingly, a need has arisen for higher package efficiency. Demand for miniaturization is the primary catalyst driving the usage of advanced packages such as chip scale packages (CSP). As compared to the ball grid array (BGA) package and thin small outline package (TSOP), the chip scale package significantly increases the packaging efficiency and has several advantages. For example, the CSP package is slightly larger than the chip, and typically, the CSP is about 20 percent larger than the chip itself. Another advantage of CSP is that the package facilitates test and burn-in before assembly as an alternative to known good die(KGD) testing. In addition, CSP can combine many of the benefits of surface mount technology (SMT), such as standardization, encapsulation, surface mount, and re-workability, with the benefits of flip chip technology, such as low inductance, high I/O count, and direct thermal path.
However, CSP has at least one disadvantage compared to conventional BGA and TSOP, namely, high cost per unit. However, this problem could be eliminated if chip-sized packages could be mass produced more easily. Therefore, there is a need in the semiconductor packaging industry for CSP using mass production techniques at the wafer-level, as is illustrated in U.S. Pat. Nos. 5,323,051, 5,925,936 and 6,004,867.
For the methods of making the chip scale package at the wafer level disclosed in U.S. Pat. Nos. 5,323,051 and the U.S. Pat. No. 5,925,936, the methods substantially comprise the steps of: a) encapsulating an active surface of a wafer; b) grinding the encapsulated wafer to expose the bumps on the active surface of the wafer and to obtain the predetermined thickness; and c) dicing the encapsulated wafer according to the exposed bump as positioning reference marks.
In the above mentioned patents, because the scribe lines is covered by molding compound on the wafer surface after encapsulating, the exposed bumps are utilized as the positioning reference marks for dicing the encapsulated wafer. But the exposed bumps of the individual chip or dice is too tiny to provide an obvious positioning reference mark which is easily detected by the positioning device of the dicing machine or apparatus. Hence, the positioning device of the dicing machine or apparatus is often positioned in error.
U.S. Pat. No. 6,004,867, entitled xe2x80x9cChip-size Package Assembled Using Mass Production Techniques At The Wafer-Levelxe2x80x9d issued on Dec. 21, 1999 to Kim et al., discloses a chip-size package technique at wafer level, wherein a substrate is attached to an active surface of a packaged wafer, the substrate includes grooves or index patterns corresponding to the scribe lines, and the grooves or index patterns in the substrate will be exposed by grinding such that the exposed grooves or index patterns are utilized as positioning reference marks for dicing the wafer. However, according to the process of Kim""s 867 Patent, the wafer requires additional attachment of the substrate for dicing, which fails to fulfill the requirements of chip scale package.
Hence, a need exists for a semiconductor package that provides a method of making the chip scale package at the wafer level to retain obvious scribe lines after the wafer is encapsulated by molding compound such that the dicing machine can be easily and accurately positioned in dicing process of the chip scale package so as to overcome the above mentioned drawback.
It is a primary object of the present invention to provide a method of manufacturing chip scale package at the wafer level for mass production so as to reduce the cost of manufacturing chip scale package. It is another object of the present invention to provide a method of manufacturing chip scale package at the wafer level to retain obvious scribe lines after the wafer is encapsulated by molding compound such that the dicing machine can be easily and accurately positioned in dicing process of the chip scale package.
In order to achieve the objects mentioned hereinabove, the method of manufacturing chip scale packages at wafer level according to an embodiment of the present invention comprises the step of:
a) providing a wafer having an active and a back side surface, the active surface of the wafer having a plurality of scribe lines to defining individual chips, and each chip having a plurality of electrodes;
b) forming a dam enclosing the perimeter of the wafer;
c) filling the area enclosed by the dam with molding compound to encapsulate the active surface of the wafer;
d) removing the dam to expose the covered scribe lines on the active surface of the wafer; and
e) dicing the wafer according to the exposed scribe lines as positioning reference marks.
According to another embodiment of the present invention, the dam is form on the active surface of the wafer spaced a predetermined distance from the perimeter of the wafer to expose the scribe lines such that the scribe lines will be exposed without removing the dam. Therefore, since the method of manufacturing chip scale packages at wafer level according to the present invention will expose the scribe lines during the manufacturing process, the wafer can be accurately diced according to the exposed scribe lines as positioning reference marks.